• Up to 1,200 user I/Os • Wide selection of I/O standards from 1.2V to 3.3V
• Extremely high-performance − Up to 800 Mb/s HSTL and SSTL (on all single-ended I/Os) − Up to 1.25 Gb/s LVDS (on all differential I/O pairs) • True differential termination on-chip • Same edge capture at input and output I/Os • Extensive memory interface support
• Up to six Clock Management Tiles (CMTs) − Each CMT contains two DCMs and one PLL—up to eighteen total clock generators − Flexible DCM-to-PLL or PLL-to-DCM cascade − Precision clock deskew and phase shift − Flexible frequency synthesis − Multiple operating modes to ease performance trade-off decisions − Improved maximum input/output frequency − Fine-grained phase shifting resolution − Input jitter filtering − Low-power operation − Wide phase shift range
• Flexible configuration options − SPI and Parallel FLASH interface − Multi-bitstream support with dedicated fallback reconfiguration logic − Auto bus width detection capability
