CHUANGXINDA ELECTRONICS-TECH CO., LIMITED

CHUANGXINDA ELECTRONICS-TECH CO., LIMITED

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5SGXMABN2F45I2LN 850mV 840 I/O Stratix V GX

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CHUANGXINDA ELECTRONICS-TECH CO., LIMITED
City:shenzhen
Province/State:guangdong
Country/Region:china
Contact Person:CXDA-FPGA
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5SGXMABN2F45I2LN 850mV 840 I/O Stratix V GX

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Brand Name :Intel / Altera
Model Number :5SGXMABN2F45I2LN
Certification :Lead free / RoHS Compliant
MOQ :1 pcs
Price :USD 16000-20000 pcs
Payment Terms :T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :108 pcs
Delivery Time :3-5 Day
Packaging Details :International Standard Packaging
Category :IC FPGA
Condition :Original 100%,Brand New and Original,New
Series :Stratix V GX
Number of Logic Array Blocks - LABs :359200
Number of I/Os :840 I/O
Operating Supply Voltage :850 mV
Package / Case :FBGA-1932
Data Rate :14.1 Gb/s
Service :BOM Kitting
Lead time :In Stock,contact us
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5SGXMABN2F45I2LN ALTERA FPGA Chip FBGA-1932 840 I/O Stratix V GX

Product Attribute Attribute Value
Intel
FPGA - Field Programmable Gate Array
Stratix V GX
952000
359200
840 I/O
850 mV
- 40 C
+ 85 C
SMD/SMT
FBGA-1932
Tray
Data Rate: 14.1 Gb/s
Series: Stratix V GX 5SGXAB
Brand: Intel / Altera
Moisture Sensitive: Yes
Number of Transceivers: 48 Transceiver
Product Type: FPGA - Field Programmable Gate Array
Factory Pack Quantity: 12
Subcategory: Programmable Logic ICs
Total Memory: 62.96 Mbit
Tradename: Stratix V FPGA
Part # Aliases: 966585

Stratix V Features Summary• 28-nm TSMC process technology
• Enhanced ALM with four registers
• Improved routing architecture reduces congestion and improves compile times
• M20K: 20-Kbit with hard error correction code (ECC)
• MLAB: 640-bit
• Up to 600 MHz performance
• New native 27x27 multiply mode
• 64-bit accumulator and cascade for systolic finite impulse responses (FIRs)
• Embedded internal coefficient memory
• Pre-adder/subtractor improves efficiency
• 1.6-Gbps LVDS
• 1,066-MHz external memory interface
• On-chip termination (OCT)
• 1.2-V to 3.3-V interfacing for all Stratix V devices
• PCIe Gen3, Gen2, and Gen1 complete protocol stack, x1/x2/x4/x8 end point and root port
• Interlaken physical coding sublayer (PCS)
• Gigabit Ethernet (GbE) and XAUI PCS
• 10G Ethernet PCS
• Serial RapidIO® (SRIO) PCS
• Common Public Radio Interface (CPRI) PCS
• Gigabit Passive Optical Networking (GPON) PCS



5SGXMABN2F45I2LN 850mV 840 I/O Stratix V GX

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