Payment Terms :T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :120 pcs
Delivery Time :3-5 Day
Packaging Details :International Standard Packaging
Category :IC FPGA
Condition :Original 100%,Brand New and Original,New
Number of Logic Array Blocks - LABs :11648
Number of I/Os :920 I/O
Package / Case :BGA-1932
Data Rate :600 Mb/s to 8.5 Gb/s
Series :Stratix IV GX
Maximum Operating Frequency :600 MHz
Service :BOM Kitting
Lead time :In Stock,contact us
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EP4SGX290NF45C2N ALTERA FPGA Chip BGA-1932 920 I/O Stratix IV GX
Product Attribute
Attribute Value
Intel
FPGA - Field Programmable Gate Array
Stratix IV GX
291200
11648
920 I/O
900 mV
0 C
+ 70 C
SMD/SMT
FBGA-1932
Tray
Data Rate:
600 Mb/s to 8.5 Gb/s
Series:
Stratix IV GX
Brand:
Intel / Altera
Maximum Operating Frequency:
600 MHz
Moisture Sensitive:
Yes
Number of Transceivers:
48 Transceiver
Product Type:
FPGA - Field Programmable Gate Array
Factory Pack Quantity:
12
Subcategory:
Programmable Logic ICs
Total Memory:
17248 kbit
Tradename:
Stratix
Part # Aliases:
972031
Stratix IV GX devices provide up to 48 full-duplex CDR-based transceiver channels per device:
■ Thirty-two out of the 48 transceiver channels have dedicated physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry and support data rates between 600 Mbps and 8.5 Gbps ■ The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbp ■ Stratix IV GX—PCIe Gen1 and Gen2, GbE, Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, GPON, SAS/SATA, HyperTransport 1.0 and 3.0, and Interlaken ■ Stratix IV GT—40G/100G Ethernet, SFI-S, Interlaken, SFI-5.1, Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, 3G-SDI, and Fibre Channel ■ Extremely flexible and easy-to-configure transceiver data path to implement proprietary protocols ■ PCIe Support ■ Complete PCIe Gen1 and Gen2 protocol stack solution compliant to PCI Express base specification 2.0 that includes PHY-MAC, Data Link, and transaction layer circuitry embedded in PCI Express hard IP blocks
