Payment Terms :T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :120 pcs
Delivery Time :3-5 Day
Packaging Details :International Standard Packaging
Category :IC FPGA
Condition :Original 100%,Brand New and Original,New
Number of Logic Array Blocks - LABs :21248
Number of I/Os :744 I/O
Package / Case :BGA-1517
Data Rate :600 Mb/s to 8.5 Gb/s
Series :Stratix IV GX
Maximum Operating Frequency :600 MHz
Service :BOM Kitting
Lead time :In Stock,contact us
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EP4SGX530KH40C4N ALTERA FPGA Chip BGA-1517 744 I/O Stratix IV GX
Product Attribute
Attribute Value
Intel
FPGA - Field Programmable Gate Array
Stratix IV GX
531200
21248
744 I/O
900 mV
0 C
+ 70 C
SMD/SMT
BGA-1517
Tray
Data Rate:
600 Mb/s to 8.5 Gb/s
Series:
Stratix IV GX
Brand:
Intel / Altera
Maximum Operating Frequency:
600 MHz
Moisture Sensitive:
Yes
Number of Transceivers:
36 Transceiver
Product Type:
FPGA - Field Programmable Gate Array
Factory Pack Quantity:
12
Subcategory:
Programmable Logic ICs
Total Memory:
27376 kbit
Tradename:
Stratix
Part # Aliases:
974500
The Stratix IV device family contains three optimized variants to meet different application requirements:
■ Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively ■ Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken ■ Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality ■ Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium ■ Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel ■ 72,600 to 813,050 equivalent LEs per device ■ 7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers ■ High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz
