CHUANGXINDA ELECTRONICS-TECH CO., LIMITED

CHUANGXINDA ELECTRONICS-TECH CO., LIMITED

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EP2S90F780C4N 620mA 534 I/O ALTERA FPGA Chip

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Province/State:guangdong
Country/Region:china
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EP2S90F780C4N 620mA 534 I/O ALTERA FPGA Chip

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Brand Name :Intel / Altera
Model Number :EP2S90F780C4N
Certification :Lead free / RoHS Compliant
MOQ :1 pcs
Price :USD 4500-5000 pcs
Payment Terms :T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :318 pcs
Delivery Time :3-5 Day
Packaging Details :International Standard Packaging
Category :IC FPGA
Condition :Original 100%,Brand New and Original,New
Number of Logic Array Blocks - LABs :4548
Number of I/Os :534 I/O
Package / Case :FBGA-780
Data Rate :600 Mb/s to 6.375 Gb/s
Series :Stratix II
Operating Supply Current :620 mA
Service :BOM Kitting
Lead time :In Stock,contact us
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EP2S90F780C4N ALTERA FPGA Chip FBGA-780 534 I/O Stratix II

Product Attribute Attribute Value
Intel
FPGA - Field Programmable Gate Array
Stratix II
60440
4548
534 I/O
1.2 V
0 C
+ 70 C
SMD/SMT
FBGA-780
Tray
Series: Stratix II EP2S90
Brand: Intel / Altera
Moisture Sensitive: Yes
Operating Supply Current: 620 mA
Product Type: FPGA - Field Programmable Gate Array
Factory Pack Quantity: 36
Subcategory: Programmable Logic ICs
Total Memory: 4520488 bit
Tradename: Stratix II
Part # Aliases: 973077

The Stratix II family offers the following features:
■ New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency
■ Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources
■ TriMatrixmemory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers
■ High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
■ Up to 16 global clocks with 24 clocking resources per device region
■ Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode
■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting



EP2S90F780C4N 620mA 534 I/O ALTERA FPGA Chip

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