Payment Terms :T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :186 pcs
Delivery Time :3-5 Day
Packaging Details :International Standard Packaging
Category :Programmable Logic ICs
Condition :Original 100%,Brand New and Original,New
Number of I/Os :680 I/O
Product :Virtex-5
Package / Case :FBGA-1738
Distributed RAM :1240 kbit
Embedded Block RAM - EBR :8208 kbit
Maximum Operating Frequency :550 MHz
Service :BOM Kitting
Lead time :In Stock,contact us
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XC5VFX100T-2FF1738C IC FPGA FBGA-1738 680 I/O 550 MHz Virtex-5
Product Attribute
Attribute Value
Xilinx
FPGA - Field Programmable Gate Array
Virtex-5
680 I/O
1 V
0 C
+ 85 C
SMD/SMT
FCBGA-1738
Data Rate:
6.5 Gb/s
Series:
XC5VFX100T
Brand:
Xilinx
Distributed RAM:
1240 kbit
Embedded Block RAM - EBR:
8208 kbit
Maximum Operating Frequency:
550 MHz
Moisture Sensitive:
Yes
Number of Transceivers:
16 Transceiver
Product Type:
FPGA - Field Programmable Gate Array
Factory Pack Quantity:
1
Subcategory:
Programmable Logic ICs
Tradename:
Virtex
Summary of Virtex-5 FPGA Features
• RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s − LXT and SXT Platforms
• RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s − TXT and FXT Platforms
• PowerPC 440 Microprocessors − FXT Platform only − RISC architecture − 7-stage pipeline − 32-Kbyte instruction and data caches included − Optimized processor interface structure (crossbar)
• 65-nm copper CMOS process technology • 1.0V core voltage • High signal-integrity flip-chip packaging available in standard or Pb-free package options
• System Monitoring capability on all devices − On-chip/Off-chip thermal monitoring − On-chip/Off-chip power supply monitoring − JTAG access to all monitored quantities
• Integrated Endpoint blocks for PCI Express Designs − LXT, SXT, TXT, and FXT Platforms − Compliant with the PCI Express Base Specification 1.1 − x1, x4, or x8 lane support per block − Works in conjunction with RocketIO™ transceivers
The function generators are configurable as 6-input LUTs or dual-output 5-input LUTs. SLICEMs in some CLBs can be configured to operate as 32-bit shift registers (or 16-bit x 2 shift registers) or as 64-bit distributed RAM. In addition, the four storage elements can be configured as either edge-triggered D-type flip-flops or level sensitive latches. Each CLB has internal fast interconnect and connects to a switch matrix to access general routing resources.
