Payment Terms :T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :400 pcs
Delivery Time :3-5 Day
Packaging Details :International Standard Packaging
Category :Programmable Logic ICs
Condition :Original 100%,Brand New and Original,New
Number of I/Os :448 I/O
Product :Virtex-4
Package / Case :FBGA-668
Distributed RAM :168 kbit
Embedded Block RAM - EBR :1296 kbit
Maximum Operating Frequency :500 MHz
Service :BOM Kitting
Lead time :In Stock,contact us
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XC4VLX25-11FF668I IC FPGA FBGA-668 448 I/O 500 MHz Virtex-4
Product Attribute
Attribute Value
Xilinx
FPGA - Field Programmable Gate Array
Virtex-4
24192
448 I/O
1.2 V
- 40 C
+ 100 C
SMD/SMT
FBGA-668
Series:
XC4VLX25
Brand:
Xilinx
Distributed RAM:
168 kbit
Embedded Block RAM - EBR:
1296 kbit
Maximum Operating Frequency:
500 MHz
Moisture Sensitive:
Yes
Product Type:
FPGA - Field Programmable Gate Array
Factory Pack Quantity:
1
Subcategory:
Programmable Logic ICs
Tradename:
Virtex
Summary of Virtex-4 FPGA Features
Virtex-4 devices are user-programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs. Virtex-4 devices implement the following functionality:
• I/O blocks provide the interface between package pins and the internal configurable logic. Most popular and leading-edge I/O standards are supported by programmable I/O blocks (IOBs). The IOBs are enhanced for source-synchronous applications. Source-synchronous optimizations include per-bit deskew, data serializer/deserializer, clock dividers, and dedicated local clocking resources.
• Configurable Logic Blocks (CLBs), the basic logic elements for Xilinx FPGAs, provide combinatorial and synchronous logic as well as distributed memory and SRL16 shift register capability.
• Block RAM modules provide flexible 18Kbit true dual-port RAM, that are cascadable to form larger memory blocks. In addition, Virtex-4 FPGA block RAMs contain optional programmable FIFO logic for increased device utilization.
• Cascadable embedded XtremeDSP slices with 18-bit x 18-bit dedicated multipliers, integrated Adder, and 48-bit accumulator.
• Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for clock distribution delay compensation, clock multiplication/division, and coarse-/fine-grained clock phase shifting.
