XC6VSX315T-2FFG1759I IC FPGA FCBGA-1759 Virtex-6 720 I/O
| Product Attribute | Attribute Value |
| Xilinx |
| FPGA - Field Programmable Gate Array |
| Virtex-6 |
| 314880 |
| 720 I/O |
| 1 V |
| - 40 C |
| + 100 C |
| SMD/SMT |
| FCBGA-1759 |
| Data Rate: | 6.6 Gb/s |
| Series: | XC6VSX315T |
| Brand: | Xilinx |
| Distributed RAM: | 5090 kbit |
| Embedded Block RAM - EBR: | 25344 kbit |
| Maximum Operating Frequency: | 1600 MHz |
| Moisture Sensitive: | Yes |
| Number of Transceivers: | 24 Transceiver |
| Product Type: | FPGA - Field Programmable Gate Array |
| Factory Pack Quantity: | 1 |
| Subcategory: | Programmable Logic ICs |
| Tradename: | Virtex |
Summary of Virtex-6 FPGA Features
• Three sub-families:
• Virtex-6 LXT FPGAs: High-performance logic with advanced serial connectivity
• Virtex-6 SXT FPGAs: Highest signal processing capability with advanced serial connectivity
• Virtex-6 HXT FPGAs: Highest bandwidth serial connectivity
• Compatibility across sub-families
• LXT and SXT devices are footprint compatible in the same package
• Advanced, high-performance FPGA Logic
• High-performance parallel SelectIO™ technology
• 1.2 to 2.5V I/O operation
• Source-synchronous interfacing using ChipSync™ technology
• Digitally controlled impedance (DCI) active termination
• Flexible fine-grained I/O banking
• High-speed memory interface support with integrated write-leveling capability
• Advanced DSP48E1 slices
• 25 x 18, two's complement multiplier/accumulator
• Optional pipelining
• New optional pre-adder to assist filtering applications
• Optional bitwise logic functionality
• Dedicated cascade connections
• Flexible configuration options
• SPI and Parallel Flash interface
• Multi-bitstream support with dedicated fallback reconfiguration logic
• Automatic bus width detection
• System Monitor capability on all devices
• On-chip/off-chip thermal and supply voltage monitoring
• 36-Kb block RAM/FIFOs
• Dual-port RAM blocks
• Programmable
- Dual-port widths up to 36 bits
- Simple dual-port widths up to 72 bits
• Enhanced programmable FIFO logic
• Built-in optional error-correction circuitry
• Optionally use each block as two independent 18 Kb blocks
