Payment Terms :T/T, Western Union, Paypal, Trade Assurance, Credit Card
Supply Ability :240 pcs
Delivery Time :3-5 Day
Packaging Details :International Standard Packaging
Category :Programmable Logic ICs
Condition :Original 100%,Brand New and Original,New
Number of I/Os :600 I/O
Product :Virtex-6
Package / Case :FCBGA-1156
Distributed RAM :1740 kbit
Embedded Block RAM - EBR :9504 kbit
Maximum Operating Frequency :1600 MHz
Service :BOM Kitting
Lead time :In Stock,contact us
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XC6VLX130T-2FF1156C IC FPGA FCBGA-1156 Virtex-6 6.6 Gb/s
Product Attribute
Attribute Value
Xilinx
FPGA - Field Programmable Gate Array
Virtex-6
128000
600 I/O
1 V
0 C
+ 85 C
SMD/SMT
FCBGA-1156
Data Rate:
6.6 Gb/s
Series:
XC6VLX130T
Brand:
Xilinx
Distributed RAM:
1740 kbit
Embedded Block RAM - EBR:
9504 kbit
Maximum Operating Frequency:
1600 MHz
Moisture Sensitive:
Yes
Number of Transceivers:
20 Transceiver
Product Type:
FPGA - Field Programmable Gate Array
Factory Pack Quantity:
24
Subcategory:
Programmable Logic ICs
Tradename:
Virtex
Summary of Virtex-6 FPGA Features
• Three sub-families: • Virtex-6 LXT FPGAs: High-performance logic with advanced serial connectivity • Virtex-6 SXT FPGAs: Highest signal processing capability with advanced serial connectivity • Virtex-6 HXT FPGAs: Highest bandwidth serial connectivity • Compatibility across sub-families • LXT and SXT devices are footprint compatible in the same package • JTAG access to all monitored quantities • Integrated interface blocks for PCI Express® designs • Compliant to the PCI Express Base Specification 2.0 • Gen1 (2.5 Gb/s) and Gen2 (5 Gb/s) support with GTX transceivers • Endpoint and Root Port capable • x1, x2, x4, or x8 lane support per block • GTX transceivers: up to 6.6 Gb/s • Data rates below 480 Mb/s supported by oversampling in FPGA logic. • GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s • Integrated 10/100/1000 Mb/s Ethernet MAC block • High-speed memory interface support with integrated write-leveling capability • Advanced DSP48E1 slices • 25 x 18, two's complement multiplier/accumulator • Optional pipelining • New optional pre-adder to assist filtering applications • Optional bitwise logic functionality • Dedicated cascade connections • Flexible configuration options • SPI and Parallel Flash interface • Multi-bitstream support with dedicated fallback reconfiguration logic • Automatic bus width detection • System Monitor capability on all devices • On-chip/off-chip thermal and supply voltage • 36-Kb block RAM/FIFOs • Dual-port RAM blocks • Programmable - Dual-port widths up to 36 bits - Simple dual-port widths up to 72 bits • Enhanced programmable FIFO logic • Built-in optional error-correction circuitry • Optionally use each block as two independent 18 Kb blocks
